dlt645_comm.c 57 KB

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  1. #include "plt.h"
  2. #define DELAY_CNT (200) // 10ms * DELAY_CNT
  3. static unsigned char dlt645_cal_chksum(int old_chk_sum, char *buf, int buf_sz)
  4. {
  5. unsigned int SumVal = old_chk_sum;
  6. int i;
  7. for (i = 0; i < buf_sz; i++)
  8. {
  9. SumVal += buf[i];
  10. }
  11. return (SumVal & 0xFF);
  12. }
  13. #define METER_STX 0x68
  14. #define ADR 0xaa
  15. #define METER_ADRLEN 6
  16. #define METER_EDX 0x16
  17. static void dlt645_pack_d07_frame(int idx, unsigned long inRulerID)
  18. {
  19. int i;
  20. struct dlt645_t *dev = &dlt645[idx];
  21. int chan_idx = dev->comm.chanidx;
  22. // struct chan_t* chan = &sta.chan[chan_idx];
  23. S_D07_RULER_INFO info = {0};
  24. char dump_buf[1024];
  25. int ret = get_d07_ruler_info(inRulerID, &info);
  26. if (ret != E_D07_OK)
  27. {
  28. log_dbg("%s, invalid ruler id", __func__);
  29. return;
  30. }
  31. unsigned char ucCtrl = 0;
  32. S_D07_CTRL_CODE stCtrl = {0};
  33. int dir = 0;
  34. char addr[64] = {0}; // 地址
  35. S_D07_PACK_FRAME pack_frame = {0};
  36. int length = 0;
  37. char buffer[256] = {0};
  38. chan_serial_ringbuffer_element_t e_arr[256];
  39. char data[256] = {0};
  40. char user[256] = {0};
  41. F_D07_RULER_TRANS func = NULL;
  42. strcpy(addr, dev->szaddr);
  43. dir = E_D07_CTRL_DIR_S2M;
  44. stCtrl.direct = (E_D07_CTRL_DIR)dir;
  45. func = info.func;
  46. if (info.type == E_D07_RULER_TYPE_COMB_HAVE_POWER_TOTAL)
  47. {
  48. sprintf(user, "%6.2f", dev->com_active_e / dev->pratio);
  49. }
  50. else if (info.type == E_D07_RULER_TYPE_FORTH_HAVE_POWER_TOTAL)
  51. {
  52. sprintf(user, "%6.2f", dev->pos_active_e / dev->pratio);
  53. }
  54. else if (info.type == E_D07_RULER_TYPE_BACK_HAVE_POWER_TOTAL)
  55. {
  56. sprintf(user, "%6.2f", dev->neg_active_e / dev->pratio);
  57. }
  58. else if (info.type == E_D07_RULER_TYPE_PHASE_A_VOLT)
  59. {
  60. sprintf(user, "%3.1f", dev->ua / dev->vratio);
  61. }
  62. else if (info.type == E_D07_RULER_TYPE_PHASE_B_VOLT)
  63. {
  64. sprintf(user, "%3.1f", dev->ub / dev->vratio);
  65. }
  66. else if (info.type == E_D07_RULER_TYPE_PHASE_C_VOLT)
  67. {
  68. sprintf(user, "%3.1f", dev->uc / dev->vratio);
  69. }
  70. else if (info.type == E_D07_RULER_TYPE_PHASE_A_ELEC)
  71. {
  72. sprintf(user, "%3.3f", dev->ia / dev->cratio);
  73. }
  74. else if (info.type == E_D07_RULER_TYPE_PHASE_B_ELEC)
  75. {
  76. sprintf(user, "%3.3f", dev->ib / dev->cratio);
  77. }
  78. else if (info.type == E_D07_RULER_TYPE_PHASE_C_ELEC)
  79. {
  80. sprintf(user, "%3.3f", dev->ic / dev->cratio);
  81. }
  82. else if (info.type == E_D07_RULER_TYPE_INSTANT_HAVE_POWER_RATE_TOTAL)
  83. {
  84. sprintf(user, "%2.4f", (double)dev->com_active_p / dev->pratio);
  85. }
  86. else if (info.type == E_D07_RULER_TYPE_UNKNOWN)
  87. {
  88. log_dbg("%s, info.type == E_D07_RULER_TYPE_UNKNOWN", __func__);
  89. return;
  90. }
  91. else
  92. {
  93. log_dbg("%s, TYPE_UNKNOWN", __func__);
  94. return;
  95. }
  96. func(E_D07_TRANS_U2F, user, data);
  97. // log_dbg("%s, user:%s, data:%s", __func__, user, data);
  98. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  99. pack_frame.data = data;
  100. pack_frame.data_len = info.len + 4;
  101. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl); // 将结构封装成字节
  102. if (ret != E_D07_OK)
  103. {
  104. log_dbg("%s, \ntrans_d07ctrl_struct2char failed %d\n", __func__, ret);
  105. return;
  106. }
  107. pack_frame.ruler_id = inRulerID;
  108. pack_frame.ctrl_code = ucCtrl;
  109. memcpy(pack_frame.address, addr, 13);
  110. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  111. if (ret != E_D07_OK)
  112. {
  113. log_dbg("%s, \npack frame failed %d\n", __func__, ret);
  114. return;
  115. }
  116. for (i = 0; i < length; i++)
  117. {
  118. e_arr[i].c = buffer[i];
  119. }
  120. // misc_dump(dump_buf, buffer, length);
  121. // log_dbg("%s, try to send %d bytes:%s", __func__, length, dump_buf);
  122. chan_lock(chan_idx);
  123. chan_serial_txrb_queue_arr(chan_idx, e_arr, length);
  124. chan_unlock(chan_idx);
  125. }
  126. static void dlt645_handle_d07_frame(int idx)
  127. {
  128. int i, j = 0;
  129. int ret = 0;
  130. S_D07_UNPACK stUnPack = {0};
  131. S_D07_RULER_INFO info = {0};
  132. struct dlt645_t *dev = &dlt645[idx];
  133. char *buf = dev->recvbuf;
  134. int len = dev->recvcnt;
  135. ret = unpack_d07_frame(buf, len, &stUnPack);
  136. if (ret != E_D07_OK)
  137. {
  138. log_dbg("%s, \n unpack fail! (error = %d : ", __func__, ret);
  139. switch (ret)
  140. {
  141. case E_D07_ERRO_FRAME_UNCOMP:
  142. log_dbg("%s, incomplete frame)\n", __func__);
  143. break;
  144. case E_D07_ERRO_FRAME_0x68:
  145. log_dbg("%s, start byte 0x68 possition error)\n", __func__);
  146. break;
  147. case E_D07_ERRO_FRAME_CHECK_SUM:
  148. log_dbg("%s, chksum err)\n", __func__);
  149. break;
  150. case E_D07_ERRO_FRAME_END_0x16:
  151. log_dbg("%s, end byte 0x16 err)\n", __func__);
  152. break;
  153. default:
  154. break;
  155. }
  156. return;
  157. }
  158. if (strcmp(stUnPack.address, dev->szaddr) == 0)
  159. {
  160. dlt645_pack_d07_frame(idx, stUnPack.ruler_id);
  161. }
  162. else
  163. {
  164. log_dbg("%s, addr not match: %s - %s", __func__, stUnPack.address, dev->szaddr);
  165. }
  166. }
  167. static void dlt645_proc_recv(int idx)
  168. {
  169. struct dlt645_t *dev = &dlt645[idx];
  170. int chan_idx = dev->comm.chanidx;
  171. // struct chan_t* chan = &sta.chan[chan_idx];
  172. size_t needprocess = 0;
  173. int nprocess = 0;
  174. chan_serial_ringbuffer_element_t e_arr[128];
  175. int i;
  176. char recvbyte;
  177. int *st = &dev->recvst;
  178. int *recvcnt = &dev->recvcnt;
  179. int *recvcnt2 = &dev->recvcnt2;
  180. char *recvbuf = dev->recvbuf;
  181. int *tick = &dev->tick;
  182. int *dl = &dev->dl;
  183. unsigned char chksum = 0;
  184. S_D07_UNPACK unpack;
  185. chan_lock(chan_idx);
  186. needprocess = chan_serial_rxrb_num_items(chan_idx);
  187. if (needprocess > 0)
  188. {
  189. nprocess = (needprocess > sizeof(e_arr) / sizeof(chan_serial_ringbuffer_element_t)) ? (sizeof(e_arr) / sizeof(chan_serial_ringbuffer_element_t)) : needprocess;
  190. chan_serial_rxrb_dequeue_arr(chan_idx, e_arr, nprocess);
  191. // log_dbg("%s, got %d bytes", __func__, nprocess);
  192. }
  193. chan_unlock(chan_idx);
  194. if (nprocess > 0)
  195. {
  196. for (i = 0; i < nprocess; i++)
  197. {
  198. recvbyte = e_arr[i].c;
  199. // log_dbg("%s, st:%d, got %02X-%c", __func__, *st, recvbyte,recvbyte);
  200. switch (*st)
  201. {
  202. case MRECV_WAIT4STX:
  203. if (recvbyte == METER_STX)
  204. {
  205. *recvcnt = 0;
  206. recvbuf[(*recvcnt)++] = recvbyte;
  207. *st = MRECV_ADDR;
  208. *recvcnt2 = 0;
  209. *tick = 0;
  210. }
  211. break;
  212. case MRECV_ADDR:
  213. recvbuf[(*recvcnt)++] = recvbyte;
  214. if (++(*recvcnt2) == METER_ADRLEN)
  215. {
  216. *st = MRECV_STX2;
  217. *tick = 0;
  218. }
  219. break;
  220. case MRECV_STX2:
  221. if (recvbyte == METER_STX)
  222. {
  223. recvbuf[(*recvcnt)++] = recvbyte;
  224. *st = MRECV_CTRL;
  225. *tick = 0;
  226. }
  227. else
  228. {
  229. *st = MRECV_WAIT4STX;
  230. }
  231. break;
  232. case MRECV_CTRL:
  233. recvbuf[(*recvcnt)++] = recvbyte;
  234. *st = MRECV_DL;
  235. *tick = 0;
  236. break;
  237. case MRECV_DL:
  238. recvbuf[(*recvcnt)++] = recvbyte;
  239. *st = MRECV_D;
  240. *tick = 0;
  241. *recvcnt2 = 0;
  242. *dl = recvbyte;
  243. break;
  244. case MRECV_D:
  245. recvbuf[(*recvcnt)++] = recvbyte;
  246. if (++(*recvcnt2) == *dl)
  247. {
  248. *st = MRECV_CS;
  249. *tick = 0;
  250. }
  251. break;
  252. case MRECV_CS:
  253. recvbuf[(*recvcnt)++] = recvbyte;
  254. *st = MRECV_ETX;
  255. *tick = 0;
  256. break;
  257. case MRECV_ETX:
  258. recvbuf[(*recvcnt)++] = recvbyte;
  259. chksum = dlt645_cal_chksum(0, recvbuf, *recvcnt - 2);
  260. if (chksum == recvbuf[*recvcnt - 2])
  261. { // chksum ok
  262. // log_dbg("%s, get cmd frame", __func__);
  263. dlt645_handle_d07_frame(idx);
  264. }
  265. else
  266. {
  267. log_dbg("%s, chksum err %d/%d", __func__, chksum, recvbuf[*recvcnt - 2]);
  268. }
  269. *st = MRECV_WAIT4STX;
  270. break;
  271. }
  272. }
  273. }
  274. else
  275. {
  276. if ((*tick)++ > 100)
  277. {
  278. *st = MRECV_WAIT4STX;
  279. }
  280. }
  281. }
  282. static int dlt645_recv_rsp(int idx)
  283. {
  284. struct dlt645_t *dev = &dlt645[idx];
  285. int chan_idx = dev->comm.chanidx;
  286. // struct chan_t* chan = &sta.chan[chan_idx];
  287. int needprocess = 0;
  288. int nprocess = 0;
  289. chan_serial_ringbuffer_element_t e_arr[128];
  290. int i;
  291. char recvbyte;
  292. int *st = &dev->recvst;
  293. int *recvcnt = &dev->recvcnt;
  294. int *recvcnt2 = &dev->recvcnt2;
  295. char *recvbuf = dev->recvbuf;
  296. int *tick = &dev->tick;
  297. int *dl = &dev->dl;
  298. unsigned char chksum = 0;
  299. S_D07_UNPACK unpack;
  300. int ret = -1;
  301. chan_lock(chan_idx);
  302. needprocess = chan_serial_rxrb_num_items(chan_idx);
  303. if (needprocess > 0)
  304. {
  305. nprocess = (needprocess > sizeof(e_arr) / sizeof(chan_serial_ringbuffer_element_t)) ? (sizeof(e_arr) / sizeof(chan_serial_ringbuffer_element_t)) : needprocess;
  306. chan_serial_rxrb_dequeue_arr(chan_idx, e_arr, nprocess);
  307. // log_dbg("%s, got %d bytes", __func__, nprocess);
  308. }
  309. chan_unlock(chan_idx);
  310. if (nprocess > 0)
  311. {
  312. for (i = 0; i < nprocess; i++)
  313. {
  314. recvbyte = e_arr[i].c;
  315. // log_dbg("%s, st:%d, got %02X-%c", __func__, *st, recvbyte,recvbyte);
  316. switch (*st)
  317. {
  318. case MRECV_WAIT4STX:
  319. if (recvbyte == METER_STX)
  320. {
  321. *recvcnt = 0;
  322. recvbuf[(*recvcnt)++] = recvbyte;
  323. *st = MRECV_ADDR;
  324. *recvcnt2 = 0;
  325. *tick = 0;
  326. }
  327. break;
  328. case MRECV_ADDR:
  329. recvbuf[(*recvcnt)++] = recvbyte;
  330. if (++(*recvcnt2) == METER_ADRLEN)
  331. {
  332. *st = MRECV_STX2;
  333. *tick = 0;
  334. }
  335. break;
  336. case MRECV_STX2:
  337. if (recvbyte == METER_STX)
  338. {
  339. recvbuf[(*recvcnt)++] = recvbyte;
  340. *st = MRECV_CTRL;
  341. *tick = 0;
  342. }
  343. else
  344. {
  345. *st = MRECV_WAIT4STX;
  346. }
  347. break;
  348. case MRECV_CTRL:
  349. recvbuf[(*recvcnt)++] = recvbyte;
  350. *st = MRECV_DL;
  351. *tick = 0;
  352. break;
  353. case MRECV_DL:
  354. recvbuf[(*recvcnt)++] = recvbyte;
  355. *st = MRECV_D;
  356. *tick = 0;
  357. *recvcnt2 = 0;
  358. *dl = recvbyte;
  359. break;
  360. case MRECV_D:
  361. recvbuf[(*recvcnt)++] = recvbyte;
  362. if (++(*recvcnt2) == *dl)
  363. {
  364. *st = MRECV_CS;
  365. *tick = 0;
  366. }
  367. break;
  368. case MRECV_CS:
  369. recvbuf[(*recvcnt)++] = recvbyte;
  370. *st = MRECV_ETX;
  371. *tick = 0;
  372. break;
  373. case MRECV_ETX:
  374. recvbuf[(*recvcnt)++] = recvbyte;
  375. chksum = dlt645_cal_chksum(0, recvbuf, *recvcnt - 2);
  376. if (chksum == recvbuf[*recvcnt - 2])
  377. { // chksum ok
  378. // log_dbg("%s, get cmd frame", __func__);
  379. return 0;
  380. // dlt645_handle_d07_frame(idx);
  381. }
  382. else
  383. {
  384. log_dbg("%s, chksum err %d/%d", __func__, chksum, recvbuf[*recvcnt - 2]);
  385. }
  386. *st = MRECV_WAIT4STX;
  387. break;
  388. }
  389. }
  390. }
  391. else
  392. {
  393. if ((*tick)++ > 100)
  394. {
  395. *st = MRECV_WAIT4STX;
  396. }
  397. }
  398. return ret;
  399. }
  400. int dlt645_read_com_ae(int idx)
  401. {
  402. int num = 1;
  403. struct dlt645_t *dev = &dlt645[idx];
  404. char addr[64] = {0};
  405. unsigned long inRulerID;
  406. S_D07_RULER_INFO info = {0};
  407. F_D07_RULER_TRANS func = NULL;
  408. S_D07_PACK_FRAME pack_frame = {0};
  409. S_D07_UNPACK stUnPack = {0};
  410. unsigned char ucCtrl = 0;
  411. int length = 0;
  412. char buffer[256] = {0};
  413. int i, cnt, rc;
  414. int ret = -1;
  415. chan_serial_ringbuffer_element_t e[256];
  416. // log_dbg("%s, ++", __func__);
  417. inRulerID = E_D07_RULER_TYPE_COMB_HAVE_POWER_TOTAL;
  418. ret = get_d07_ruler_info(inRulerID, &info);
  419. S_D07_CTRL_CODE stCtrl = {0};
  420. strcpy(addr, dev->szaddr);
  421. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  422. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  423. pack_frame.data_len = 4;
  424. pack_frame.data = NULL;
  425. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  426. if (ret != E_D07_OK)
  427. {
  428. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  429. ret = -1;
  430. goto leave;
  431. }
  432. pack_frame.ruler_id = inRulerID;
  433. pack_frame.ctrl_code = ucCtrl;
  434. memcpy(pack_frame.address, addr, 13);
  435. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  436. if (ret != E_D07_OK)
  437. {
  438. log_dbg("\npack frame failed %d\n", ret);
  439. ret = -1;
  440. goto leave;
  441. }
  442. // dlt645api_show_packet(length, buffer);
  443. for (i = 0; i < length; i++)
  444. {
  445. e[i].c = buffer[i];
  446. // log_dbg("%02X ", buffer[i]);
  447. }
  448. // chan_lock(dev->comm.chanidx);
  449. chan_serial_rxrb_init(dev->comm.chanidx);
  450. chan_serial_txrb_init(dev->comm.chanidx);
  451. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  452. dev->recvst = MRECV_WAIT4STX;
  453. cnt = DELAY_CNT;
  454. while (cnt-- > 0)
  455. {
  456. usleep(10000); /* 10ms */
  457. rc = dlt645_recv_rsp(idx);
  458. if (rc == 0)
  459. {
  460. break;
  461. }
  462. }
  463. // chan_unlock(dev->comm.chanidx);
  464. if (rc == 0)
  465. {
  466. // log_dbg("frame is : ");
  467. // for(i = 0; i < dev->recvcnt; i++){
  468. // log_dbg("%02X ",dev->recvbuf[i]);
  469. // }
  470. // dlt645api_debug_switch(D07_ON);
  471. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  472. // dlt645api_debug_switch(D07_OFF);
  473. if (ret != E_D07_OK)
  474. {
  475. log_dbg("\n error! (error = %d : ", ret);
  476. switch (ret)
  477. {
  478. case E_D07_ERRO_FRAME_UNCOMP:
  479. log_dbg("frame not complete)\n");
  480. break;
  481. case E_D07_ERRO_FRAME_0x68:
  482. log_dbg("start 0x68 position err)\n");
  483. break;
  484. case E_D07_ERRO_FRAME_CHECK_SUM:
  485. log_dbg("chksum error)\n");
  486. break;
  487. case E_D07_ERRO_FRAME_END_0x16:
  488. log_dbg("end 0x16 err)\n");
  489. break;
  490. default:
  491. break;
  492. }
  493. ret = -1;
  494. goto leave;
  495. }
  496. if (stUnPack.ruler_id != E_D07_RULER_TYPE_COMB_HAVE_POWER_TOTAL)
  497. {
  498. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  499. ret = -1;
  500. goto leave;
  501. }
  502. else
  503. {
  504. dev->com_active_e = stUnPack.data_unpack.fPower * dev->pratio;
  505. // log_dbg("%s, com_ae = %.2f", __func__, dev->com_active_e);
  506. ret = 0;
  507. goto leave;
  508. }
  509. }
  510. else
  511. {
  512. ret = -1;
  513. goto leave;
  514. }
  515. leave:
  516. if (ret < 0)
  517. {
  518. log_dbg("%s, --, ret:%d", __func__, ret);
  519. }
  520. return ret;
  521. }
  522. int dlt645_read_com_ap(int idx)
  523. {
  524. int num = 1;
  525. struct dlt645_t *dev = &dlt645[idx];
  526. char addr[64] = {0};
  527. unsigned long inRulerID;
  528. S_D07_RULER_INFO info = {0};
  529. F_D07_RULER_TRANS func = NULL;
  530. S_D07_PACK_FRAME pack_frame = {0};
  531. S_D07_UNPACK stUnPack = {0};
  532. unsigned char ucCtrl = 0;
  533. int length = 0;
  534. char buffer[256] = {0};
  535. int ret, i, cnt, rc;
  536. chan_serial_ringbuffer_element_t e[256];
  537. // log_dbg("%s, ++", __func__);
  538. inRulerID = E_D07_RULER_TYPE_INSTANT_HAVE_POWER_RATE_TOTAL;
  539. ret = get_d07_ruler_info(inRulerID, &info);
  540. S_D07_CTRL_CODE stCtrl = {0};
  541. strcpy(addr, dev->szaddr);
  542. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  543. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  544. pack_frame.data_len = 4;
  545. pack_frame.data = NULL;
  546. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  547. if (ret != E_D07_OK)
  548. {
  549. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  550. ret = -1;
  551. goto leave;
  552. }
  553. pack_frame.ruler_id = inRulerID;
  554. pack_frame.ctrl_code = ucCtrl;
  555. memcpy(pack_frame.address, addr, 13);
  556. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  557. if (ret != E_D07_OK)
  558. {
  559. log_dbg("\npack frame failed %d\n", ret);
  560. ret = -1;
  561. goto leave;
  562. }
  563. // dlt645api_show_packet(length, buffer);
  564. for (i = 0; i < length; i++)
  565. {
  566. e[i].c = buffer[i];
  567. // log_dbg("%02X ", buffer[i]);
  568. }
  569. // chan_lock(dev->comm.chanidx);
  570. chan_serial_rxrb_init(dev->comm.chanidx);
  571. chan_serial_txrb_init(dev->comm.chanidx);
  572. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  573. dev->recvst = MRECV_WAIT4STX;
  574. cnt = DELAY_CNT;
  575. while (cnt-- > 0)
  576. {
  577. usleep(10000); /* 10ms */
  578. rc = dlt645_recv_rsp(idx);
  579. if (rc == 0)
  580. {
  581. break;
  582. }
  583. }
  584. // chan_unlock(dev->comm.chanidx);
  585. if (rc == 0)
  586. {
  587. // log_dbg("frame is : ");
  588. // for(i = 0; i < dev->recvcnt; i++){
  589. // log_dbg("%02X ",dev->recvbuf[i]);
  590. // }
  591. // dlt645api_debug_switch(D07_ON);
  592. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  593. // dlt645api_debug_switch(D07_OFF);
  594. if (ret != E_D07_OK)
  595. {
  596. log_dbg("\n error! (error = %d : ", ret);
  597. switch (ret)
  598. {
  599. case E_D07_ERRO_FRAME_UNCOMP:
  600. log_dbg("frame not complete)\n");
  601. break;
  602. case E_D07_ERRO_FRAME_0x68:
  603. log_dbg("start 0x68 position err)\n");
  604. break;
  605. case E_D07_ERRO_FRAME_CHECK_SUM:
  606. log_dbg("chksum error)\n");
  607. break;
  608. case E_D07_ERRO_FRAME_END_0x16:
  609. log_dbg("end 0x16 err)\n");
  610. break;
  611. default:
  612. break;
  613. }
  614. ret = -1;
  615. goto leave;
  616. }
  617. if (stUnPack.ruler_id != E_D07_RULER_TYPE_INSTANT_HAVE_POWER_RATE_TOTAL)
  618. {
  619. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  620. ret = -1;
  621. goto leave;
  622. }
  623. else
  624. {
  625. dev->com_active_p = stUnPack.data_unpack.fPower * dev->pratio;
  626. // log_dbg("%s, com_ap = %.1f", __func__, dev->com_active_p);
  627. ret = 0;
  628. goto leave;
  629. }
  630. }
  631. else
  632. {
  633. ret = -1;
  634. goto leave;
  635. }
  636. leave:
  637. if (ret < 0)
  638. {
  639. log_dbg("%s, --, ret:%d", __func__, ret);
  640. }
  641. return ret;
  642. }
  643. int dlt645_read_ua(int idx)
  644. {
  645. int num = 1;
  646. struct dlt645_t *dev = &dlt645[idx];
  647. char addr[64] = {0};
  648. unsigned long inRulerID;
  649. S_D07_RULER_INFO info = {0};
  650. F_D07_RULER_TRANS func = NULL;
  651. S_D07_PACK_FRAME pack_frame = {0};
  652. S_D07_UNPACK stUnPack = {0};
  653. unsigned char ucCtrl = 0;
  654. int length = 0;
  655. char buffer[256] = {0};
  656. int ret, i, cnt, rc;
  657. chan_serial_ringbuffer_element_t e[256];
  658. // log_dbg("%s, ++", __func__);
  659. inRulerID = E_D07_RULER_TYPE_PHASE_A_VOLT;
  660. ret = get_d07_ruler_info(inRulerID, &info);
  661. S_D07_CTRL_CODE stCtrl = {0};
  662. strcpy(addr, dev->szaddr);
  663. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  664. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  665. pack_frame.data_len = 4;
  666. pack_frame.data = NULL;
  667. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  668. if (ret != E_D07_OK)
  669. {
  670. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  671. ret = -1;
  672. goto leave;
  673. }
  674. pack_frame.ruler_id = inRulerID;
  675. pack_frame.ctrl_code = ucCtrl;
  676. memcpy(pack_frame.address, addr, 13);
  677. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  678. if (ret != E_D07_OK)
  679. {
  680. log_dbg("\npack frame failed %d\n", ret);
  681. ret = -1;
  682. goto leave;
  683. }
  684. // dlt645api_show_packet(length, buffer);
  685. for (i = 0; i < length; i++)
  686. {
  687. e[i].c = buffer[i];
  688. // log_dbg("%02X ", buffer[i]);
  689. }
  690. // chan_lock(dev->comm.chanidx);
  691. chan_serial_rxrb_init(dev->comm.chanidx);
  692. chan_serial_txrb_init(dev->comm.chanidx);
  693. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  694. dev->recvst = MRECV_WAIT4STX;
  695. cnt = DELAY_CNT;
  696. while (cnt-- > 0)
  697. {
  698. usleep(10000); /* 10ms */
  699. rc = dlt645_recv_rsp(idx);
  700. if (rc == 0)
  701. {
  702. break;
  703. }
  704. }
  705. // chan_unlock(dev->comm.chanidx);
  706. if (rc == 0)
  707. {
  708. // log_dbg("frame is : ");
  709. // for(i = 0; i < dev->recvcnt; i++){
  710. // log_dbg("%02X ",dev->recvbuf[i]);
  711. // }
  712. // dlt645api_debug_switch(D07_ON);
  713. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  714. // dlt645api_debug_switch(D07_OFF);
  715. if (ret != E_D07_OK)
  716. {
  717. log_dbg("\n error! (error = %d : ", ret);
  718. switch (ret)
  719. {
  720. case E_D07_ERRO_FRAME_UNCOMP:
  721. log_dbg("frame not complete)\n");
  722. break;
  723. case E_D07_ERRO_FRAME_0x68:
  724. log_dbg("start 0x68 position err)\n");
  725. break;
  726. case E_D07_ERRO_FRAME_CHECK_SUM:
  727. log_dbg("chksum error)\n");
  728. break;
  729. case E_D07_ERRO_FRAME_END_0x16:
  730. log_dbg("end 0x16 err)\n");
  731. break;
  732. default:
  733. break;
  734. }
  735. ret = -1;
  736. goto leave;
  737. }
  738. if (stUnPack.ruler_id != E_D07_RULER_TYPE_PHASE_A_VOLT)
  739. {
  740. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  741. ret = -1;
  742. goto leave;
  743. }
  744. else
  745. {
  746. dev->ua = stUnPack.data_unpack.fPower * dev->vratio;
  747. // log_dbg("%s, ua = %.1f", __func__, dev->ua);
  748. ret = 0;
  749. goto leave;
  750. }
  751. }
  752. else
  753. {
  754. ret = -1;
  755. goto leave;
  756. }
  757. leave:
  758. if (ret < 0)
  759. {
  760. log_dbg("%s, --, ret:%d", __func__, ret);
  761. }
  762. return ret;
  763. }
  764. int dlt645_read_ub(int idx)
  765. {
  766. int num = 1;
  767. struct dlt645_t *dev = &dlt645[idx];
  768. char addr[64] = {0};
  769. unsigned long inRulerID;
  770. S_D07_RULER_INFO info = {0};
  771. F_D07_RULER_TRANS func = NULL;
  772. S_D07_PACK_FRAME pack_frame = {0};
  773. S_D07_UNPACK stUnPack = {0};
  774. unsigned char ucCtrl = 0;
  775. int length = 0;
  776. char buffer[256] = {0};
  777. int ret, i, cnt, rc;
  778. chan_serial_ringbuffer_element_t e[256];
  779. // log_dbg("%s, ++", __func__);
  780. inRulerID = E_D07_RULER_TYPE_PHASE_B_VOLT;
  781. ret = get_d07_ruler_info(inRulerID, &info);
  782. S_D07_CTRL_CODE stCtrl = {0};
  783. strcpy(addr, dev->szaddr);
  784. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  785. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  786. pack_frame.data_len = 4;
  787. pack_frame.data = NULL;
  788. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  789. if (ret != E_D07_OK)
  790. {
  791. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  792. ret = -1;
  793. goto leave;
  794. }
  795. pack_frame.ruler_id = inRulerID;
  796. pack_frame.ctrl_code = ucCtrl;
  797. memcpy(pack_frame.address, addr, 13);
  798. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  799. if (ret != E_D07_OK)
  800. {
  801. log_dbg("\npack frame failed %d\n", ret);
  802. ret = -1;
  803. goto leave;
  804. }
  805. // dlt645api_show_packet(length, buffer);
  806. for (i = 0; i < length; i++)
  807. {
  808. e[i].c = buffer[i];
  809. // log_dbg("%02X ", buffer[i]);
  810. }
  811. // chan_lock(dev->comm.chanidx);
  812. chan_serial_rxrb_init(dev->comm.chanidx);
  813. chan_serial_txrb_init(dev->comm.chanidx);
  814. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  815. dev->recvst = MRECV_WAIT4STX;
  816. cnt = DELAY_CNT;
  817. while (cnt-- > 0)
  818. {
  819. usleep(10000); /* 10ms */
  820. rc = dlt645_recv_rsp(idx);
  821. if (rc == 0)
  822. {
  823. break;
  824. }
  825. }
  826. // chan_unlock(dev->comm.chanidx);
  827. if (rc == 0)
  828. {
  829. // log_dbg("frame is : ");
  830. // for(i = 0; i < dev->recvcnt; i++){
  831. // log_dbg("%02X ",dev->recvbuf[i]);
  832. // }
  833. // dlt645api_debug_switch(D07_ON);
  834. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  835. // dlt645api_debug_switch(D07_OFF);
  836. if (ret != E_D07_OK)
  837. {
  838. log_dbg("\n error! (error = %d : ", ret);
  839. switch (ret)
  840. {
  841. case E_D07_ERRO_FRAME_UNCOMP:
  842. log_dbg("frame not complete)\n");
  843. break;
  844. case E_D07_ERRO_FRAME_0x68:
  845. log_dbg("start 0x68 position err)\n");
  846. break;
  847. case E_D07_ERRO_FRAME_CHECK_SUM:
  848. log_dbg("chksum error)\n");
  849. break;
  850. case E_D07_ERRO_FRAME_END_0x16:
  851. log_dbg("end 0x16 err)\n");
  852. break;
  853. default:
  854. break;
  855. }
  856. ret = -1;
  857. goto leave;
  858. }
  859. if (stUnPack.ruler_id != inRulerID)
  860. {
  861. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  862. ret = -1;
  863. goto leave;
  864. }
  865. else
  866. {
  867. dev->ub = stUnPack.data_unpack.fPower * dev->vratio;
  868. // log_dbg("%s, ub = %.1f", __func__, dev->ub);
  869. ret = 0;
  870. goto leave;
  871. }
  872. }
  873. else
  874. {
  875. ret = -1;
  876. goto leave;
  877. }
  878. leave:
  879. if (ret < 0)
  880. {
  881. log_dbg("%s, --, ret:%d", __func__, ret);
  882. }
  883. return ret;
  884. }
  885. int dlt645_read_uc(int idx)
  886. {
  887. int num = 1;
  888. struct dlt645_t *dev = &dlt645[idx];
  889. char addr[64] = {0};
  890. unsigned long inRulerID;
  891. S_D07_RULER_INFO info = {0};
  892. F_D07_RULER_TRANS func = NULL;
  893. S_D07_PACK_FRAME pack_frame = {0};
  894. S_D07_UNPACK stUnPack = {0};
  895. unsigned char ucCtrl = 0;
  896. int length = 0;
  897. char buffer[256] = {0};
  898. int ret, i, cnt, rc;
  899. chan_serial_ringbuffer_element_t e[256];
  900. // log_dbg("%s, ++", __func__);
  901. inRulerID = E_D07_RULER_TYPE_PHASE_C_VOLT;
  902. ret = get_d07_ruler_info(inRulerID, &info);
  903. S_D07_CTRL_CODE stCtrl = {0};
  904. strcpy(addr, dev->szaddr);
  905. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  906. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  907. pack_frame.data_len = 4;
  908. pack_frame.data = NULL;
  909. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  910. if (ret != E_D07_OK)
  911. {
  912. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  913. ret = -1;
  914. goto leave;
  915. }
  916. pack_frame.ruler_id = inRulerID;
  917. pack_frame.ctrl_code = ucCtrl;
  918. memcpy(pack_frame.address, addr, 13);
  919. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  920. if (ret != E_D07_OK)
  921. {
  922. log_dbg("\npack frame failed %d\n", ret);
  923. ret = -1;
  924. goto leave;
  925. }
  926. // dlt645api_show_packet(length, buffer);
  927. for (i = 0; i < length; i++)
  928. {
  929. e[i].c = buffer[i];
  930. // log_dbg("%02X ", buffer[i]);
  931. }
  932. // chan_lock(dev->comm.chanidx);
  933. chan_serial_rxrb_init(dev->comm.chanidx);
  934. chan_serial_txrb_init(dev->comm.chanidx);
  935. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  936. dev->recvst = MRECV_WAIT4STX;
  937. cnt = DELAY_CNT;
  938. while (cnt-- > 0)
  939. {
  940. usleep(10000); /* 10ms */
  941. rc = dlt645_recv_rsp(idx);
  942. if (rc == 0)
  943. {
  944. break;
  945. }
  946. }
  947. // chan_unlock(dev->comm.chanidx);
  948. if (rc == 0)
  949. {
  950. // log_dbg("frame is : ");
  951. // for(i = 0; i < dev->recvcnt; i++){
  952. // log_dbg("%02X ",dev->recvbuf[i]);
  953. // }
  954. // dlt645api_debug_switch(D07_ON);
  955. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  956. // dlt645api_debug_switch(D07_OFF);
  957. if (ret != E_D07_OK)
  958. {
  959. log_dbg("\n error! (error = %d : ", ret);
  960. switch (ret)
  961. {
  962. case E_D07_ERRO_FRAME_UNCOMP:
  963. log_dbg("frame not complete)\n");
  964. break;
  965. case E_D07_ERRO_FRAME_0x68:
  966. log_dbg("start 0x68 position err)\n");
  967. break;
  968. case E_D07_ERRO_FRAME_CHECK_SUM:
  969. log_dbg("chksum error)\n");
  970. break;
  971. case E_D07_ERRO_FRAME_END_0x16:
  972. log_dbg("end 0x16 err)\n");
  973. break;
  974. default:
  975. break;
  976. }
  977. ret = -1;
  978. goto leave;
  979. }
  980. if (stUnPack.ruler_id != inRulerID)
  981. {
  982. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  983. ret = -1;
  984. goto leave;
  985. }
  986. else
  987. {
  988. dev->uc = stUnPack.data_unpack.fPower * dev->vratio;
  989. // log_dbg("%s, uc = %.1f", __func__, dev->uc);
  990. ret = 0;
  991. goto leave;
  992. }
  993. }
  994. else
  995. {
  996. ret = -1;
  997. goto leave;
  998. }
  999. leave:
  1000. if (ret < 0)
  1001. {
  1002. log_dbg("%s, --, ret:%d", __func__, ret);
  1003. }
  1004. return ret;
  1005. }
  1006. int dlt645_read_ia(int idx)
  1007. {
  1008. int num = 1;
  1009. struct dlt645_t *dev = &dlt645[idx];
  1010. char addr[64] = {0};
  1011. unsigned long inRulerID;
  1012. S_D07_RULER_INFO info = {0};
  1013. F_D07_RULER_TRANS func = NULL;
  1014. S_D07_PACK_FRAME pack_frame = {0};
  1015. S_D07_UNPACK stUnPack = {0};
  1016. unsigned char ucCtrl = 0;
  1017. int length = 0;
  1018. char buffer[256] = {0};
  1019. int ret, i, cnt, rc;
  1020. chan_serial_ringbuffer_element_t e[256];
  1021. // log_dbg("%s, ++", __func__);
  1022. inRulerID = E_D07_RULER_TYPE_PHASE_A_ELEC;
  1023. ret = get_d07_ruler_info(inRulerID, &info);
  1024. S_D07_CTRL_CODE stCtrl = {0};
  1025. strcpy(addr, dev->szaddr);
  1026. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  1027. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  1028. pack_frame.data_len = 4;
  1029. pack_frame.data = NULL;
  1030. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  1031. if (ret != E_D07_OK)
  1032. {
  1033. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  1034. ret = -1;
  1035. goto leave;
  1036. }
  1037. pack_frame.ruler_id = inRulerID;
  1038. pack_frame.ctrl_code = ucCtrl;
  1039. memcpy(pack_frame.address, addr, 13);
  1040. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  1041. if (ret != E_D07_OK)
  1042. {
  1043. log_dbg("\npack frame failed %d\n", ret);
  1044. ret = -1;
  1045. goto leave;
  1046. }
  1047. // dlt645api_show_packet(length, buffer);
  1048. for (i = 0; i < length; i++)
  1049. {
  1050. e[i].c = buffer[i];
  1051. // log_dbg("%02X ", buffer[i]);
  1052. }
  1053. // chan_lock(dev->comm.chanidx);
  1054. chan_serial_rxrb_init(dev->comm.chanidx);
  1055. chan_serial_txrb_init(dev->comm.chanidx);
  1056. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  1057. dev->recvst = MRECV_WAIT4STX;
  1058. cnt = DELAY_CNT;
  1059. while (cnt-- > 0)
  1060. {
  1061. usleep(10000); /* 10ms */
  1062. rc = dlt645_recv_rsp(idx);
  1063. if (rc == 0)
  1064. {
  1065. break;
  1066. }
  1067. }
  1068. // chan_unlock(dev->comm.chanidx);
  1069. if (rc == 0)
  1070. {
  1071. // log_dbg("frame is : ");
  1072. // for(i = 0; i < dev->recvcnt; i++){
  1073. // log_dbg("%02X ",dev->recvbuf[i]);
  1074. // }
  1075. // dlt645api_debug_switch(D07_ON);
  1076. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  1077. // dlt645api_debug_switch(D07_OFF);
  1078. if (ret != E_D07_OK)
  1079. {
  1080. log_dbg("\n error! (error = %d : ", ret);
  1081. switch (ret)
  1082. {
  1083. case E_D07_ERRO_FRAME_UNCOMP:
  1084. log_dbg("frame not complete)\n");
  1085. break;
  1086. case E_D07_ERRO_FRAME_0x68:
  1087. log_dbg("start 0x68 position err)\n");
  1088. break;
  1089. case E_D07_ERRO_FRAME_CHECK_SUM:
  1090. log_dbg("chksum error)\n");
  1091. break;
  1092. case E_D07_ERRO_FRAME_END_0x16:
  1093. log_dbg("end 0x16 err)\n");
  1094. break;
  1095. default:
  1096. break;
  1097. }
  1098. ret = -1;
  1099. goto leave;
  1100. }
  1101. if (stUnPack.ruler_id != E_D07_RULER_TYPE_PHASE_A_ELEC)
  1102. {
  1103. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  1104. ret = -1;
  1105. goto leave;
  1106. }
  1107. else
  1108. {
  1109. dev->ia = stUnPack.data_unpack.fPower * dev->cratio;
  1110. // log_dbg("%s, ia = %.3f", __func__, dev->ia);
  1111. ret = 0;
  1112. goto leave;
  1113. }
  1114. }
  1115. else
  1116. {
  1117. ret = -1;
  1118. goto leave;
  1119. }
  1120. leave:
  1121. if (ret < 0)
  1122. {
  1123. log_dbg("%s, --, ret:%d", __func__, ret);
  1124. }
  1125. return ret;
  1126. }
  1127. int dlt645_read_ib(int idx)
  1128. {
  1129. int num = 1;
  1130. struct dlt645_t *dev = &dlt645[idx];
  1131. char addr[64] = {0};
  1132. unsigned long inRulerID;
  1133. S_D07_RULER_INFO info = {0};
  1134. F_D07_RULER_TRANS func = NULL;
  1135. S_D07_PACK_FRAME pack_frame = {0};
  1136. S_D07_UNPACK stUnPack = {0};
  1137. unsigned char ucCtrl = 0;
  1138. int length = 0;
  1139. char buffer[256] = {0};
  1140. int ret, i, cnt, rc;
  1141. chan_serial_ringbuffer_element_t e[256];
  1142. // log_dbg("%s, ++", __func__);
  1143. inRulerID = E_D07_RULER_TYPE_PHASE_B_ELEC;
  1144. ret = get_d07_ruler_info(inRulerID, &info);
  1145. S_D07_CTRL_CODE stCtrl = {0};
  1146. strcpy(addr, dev->szaddr);
  1147. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  1148. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  1149. pack_frame.data_len = 4;
  1150. pack_frame.data = NULL;
  1151. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  1152. if (ret != E_D07_OK)
  1153. {
  1154. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  1155. ret = -1;
  1156. goto leave;
  1157. }
  1158. pack_frame.ruler_id = inRulerID;
  1159. pack_frame.ctrl_code = ucCtrl;
  1160. memcpy(pack_frame.address, addr, 13);
  1161. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  1162. if (ret != E_D07_OK)
  1163. {
  1164. log_dbg("\npack frame failed %d\n", ret);
  1165. ret = -1;
  1166. goto leave;
  1167. }
  1168. // dlt645api_show_packet(length, buffer);
  1169. for (i = 0; i < length; i++)
  1170. {
  1171. e[i].c = buffer[i];
  1172. // log_dbg("%02X ", buffer[i]);
  1173. }
  1174. // chan_lock(dev->comm.chanidx);
  1175. chan_serial_rxrb_init(dev->comm.chanidx);
  1176. chan_serial_txrb_init(dev->comm.chanidx);
  1177. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  1178. dev->recvst = MRECV_WAIT4STX;
  1179. cnt = DELAY_CNT;
  1180. while (cnt-- > 0)
  1181. {
  1182. usleep(10000); /* 10ms */
  1183. rc = dlt645_recv_rsp(idx);
  1184. if (rc == 0)
  1185. {
  1186. break;
  1187. }
  1188. }
  1189. // chan_unlock(dev->comm.chanidx);
  1190. if (rc == 0)
  1191. {
  1192. // log_dbg("frame is : ");
  1193. // for(i = 0; i < dev->recvcnt; i++){
  1194. // log_dbg("%02X ",dev->recvbuf[i]);
  1195. // }
  1196. // dlt645api_debug_switch(D07_ON);
  1197. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  1198. // dlt645api_debug_switch(D07_OFF);
  1199. if (ret != E_D07_OK)
  1200. {
  1201. log_dbg("\n error! (error = %d : ", ret);
  1202. switch (ret)
  1203. {
  1204. case E_D07_ERRO_FRAME_UNCOMP:
  1205. log_dbg("frame not complete)\n");
  1206. break;
  1207. case E_D07_ERRO_FRAME_0x68:
  1208. log_dbg("start 0x68 position err)\n");
  1209. break;
  1210. case E_D07_ERRO_FRAME_CHECK_SUM:
  1211. log_dbg("chksum error)\n");
  1212. break;
  1213. case E_D07_ERRO_FRAME_END_0x16:
  1214. log_dbg("end 0x16 err)\n");
  1215. break;
  1216. default:
  1217. break;
  1218. }
  1219. ret = -1;
  1220. goto leave;
  1221. }
  1222. if (stUnPack.ruler_id != inRulerID)
  1223. {
  1224. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  1225. ret = -1;
  1226. goto leave;
  1227. }
  1228. else
  1229. {
  1230. dev->ib = stUnPack.data_unpack.fPower * dev->cratio;
  1231. // log_dbg("%s, ib = %.3f", __func__, dev->ib);
  1232. ret = 0;
  1233. goto leave;
  1234. }
  1235. }
  1236. else
  1237. {
  1238. ret = -1;
  1239. goto leave;
  1240. }
  1241. leave:
  1242. if (ret < 0)
  1243. {
  1244. log_dbg("%s, --, ret:%d", __func__, ret);
  1245. }
  1246. return ret;
  1247. }
  1248. int dlt645_read_ic(int idx)
  1249. {
  1250. int num = 1;
  1251. struct dlt645_t *dev = &dlt645[idx];
  1252. char addr[64] = {0};
  1253. unsigned long inRulerID;
  1254. S_D07_RULER_INFO info = {0};
  1255. F_D07_RULER_TRANS func = NULL;
  1256. S_D07_PACK_FRAME pack_frame = {0};
  1257. S_D07_UNPACK stUnPack = {0};
  1258. unsigned char ucCtrl = 0;
  1259. int length = 0;
  1260. char buffer[256] = {0};
  1261. int ret, i, cnt, rc;
  1262. chan_serial_ringbuffer_element_t e[256];
  1263. // log_dbg("%s, ++", __func__);
  1264. inRulerID = E_D07_RULER_TYPE_PHASE_C_ELEC;
  1265. ret = get_d07_ruler_info(inRulerID, &info);
  1266. S_D07_CTRL_CODE stCtrl = {0};
  1267. strcpy(addr, dev->szaddr);
  1268. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  1269. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  1270. pack_frame.data_len = 4;
  1271. pack_frame.data = NULL;
  1272. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  1273. if (ret != E_D07_OK)
  1274. {
  1275. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  1276. ret = -1;
  1277. goto leave;
  1278. }
  1279. pack_frame.ruler_id = inRulerID;
  1280. pack_frame.ctrl_code = ucCtrl;
  1281. memcpy(pack_frame.address, addr, 13);
  1282. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  1283. if (ret != E_D07_OK)
  1284. {
  1285. log_dbg("\npack frame failed %d\n", ret);
  1286. ret = -1;
  1287. goto leave;
  1288. }
  1289. // dlt645api_show_packet(length, buffer);
  1290. for (i = 0; i < length; i++)
  1291. {
  1292. e[i].c = buffer[i];
  1293. // log_dbg("%02X ", buffer[i]);
  1294. }
  1295. // chan_lock(dev->comm.chanidx);
  1296. chan_serial_rxrb_init(dev->comm.chanidx);
  1297. chan_serial_txrb_init(dev->comm.chanidx);
  1298. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  1299. dev->recvst = MRECV_WAIT4STX;
  1300. cnt = DELAY_CNT;
  1301. while (cnt-- > 0)
  1302. {
  1303. usleep(10000); /* 10ms */
  1304. rc = dlt645_recv_rsp(idx);
  1305. if (rc == 0)
  1306. {
  1307. break;
  1308. }
  1309. }
  1310. // chan_unlock(dev->comm.chanidx);
  1311. if (rc == 0)
  1312. {
  1313. // log_dbg("frame is : ");
  1314. // for(i = 0; i < dev->recvcnt; i++){
  1315. // log_dbg("%02X ",dev->recvbuf[i]);
  1316. // }
  1317. // dlt645api_debug_switch(D07_ON);
  1318. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  1319. // dlt645api_debug_switch(D07_OFF);
  1320. if (ret != E_D07_OK)
  1321. {
  1322. log_dbg("\n error! (error = %d : ", ret);
  1323. switch (ret)
  1324. {
  1325. case E_D07_ERRO_FRAME_UNCOMP:
  1326. log_dbg("frame not complete)\n");
  1327. break;
  1328. case E_D07_ERRO_FRAME_0x68:
  1329. log_dbg("start 0x68 position err)\n");
  1330. break;
  1331. case E_D07_ERRO_FRAME_CHECK_SUM:
  1332. log_dbg("chksum error)\n");
  1333. break;
  1334. case E_D07_ERRO_FRAME_END_0x16:
  1335. log_dbg("end 0x16 err)\n");
  1336. break;
  1337. default:
  1338. break;
  1339. }
  1340. ret = -1;
  1341. goto leave;
  1342. }
  1343. if (stUnPack.ruler_id != inRulerID)
  1344. {
  1345. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  1346. ret = -1;
  1347. goto leave;
  1348. }
  1349. else
  1350. {
  1351. dev->ic = stUnPack.data_unpack.fPower * dev->cratio;
  1352. // log_dbg("%s, ic = %.3f", __func__, dev->ic);
  1353. ret = 0;
  1354. goto leave;
  1355. }
  1356. }
  1357. else
  1358. {
  1359. ret = -1;
  1360. goto leave;
  1361. }
  1362. leave:
  1363. if (ret < 0)
  1364. {
  1365. log_dbg("%s, --, ret:%d", __func__, ret);
  1366. }
  1367. return ret;
  1368. }
  1369. int dlt645_read_pos_ae(int idx)
  1370. {
  1371. int num = 1;
  1372. struct dlt645_t *dev = &dlt645[idx];
  1373. char addr[64] = {0};
  1374. unsigned long inRulerID;
  1375. S_D07_RULER_INFO info = {0};
  1376. F_D07_RULER_TRANS func = NULL;
  1377. S_D07_PACK_FRAME pack_frame = {0};
  1378. S_D07_UNPACK stUnPack = {0};
  1379. unsigned char ucCtrl = 0;
  1380. int length = 0;
  1381. char buffer[256] = {0};
  1382. int ret, i, cnt, rc;
  1383. chan_serial_ringbuffer_element_t e[256];
  1384. // log_dbg("%s, ++", __func__);
  1385. inRulerID = E_D07_RULER_TYPE_FORTH_HAVE_POWER_TOTAL;
  1386. ret = get_d07_ruler_info(inRulerID, &info);
  1387. S_D07_CTRL_CODE stCtrl = {0};
  1388. strcpy(addr, dev->szaddr);
  1389. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  1390. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  1391. pack_frame.data_len = 4;
  1392. pack_frame.data = NULL;
  1393. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  1394. if (ret != E_D07_OK)
  1395. {
  1396. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  1397. ret = -1;
  1398. goto leave;
  1399. }
  1400. pack_frame.ruler_id = inRulerID;
  1401. pack_frame.ctrl_code = ucCtrl;
  1402. memcpy(pack_frame.address, addr, 13);
  1403. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  1404. if (ret != E_D07_OK)
  1405. {
  1406. log_dbg("\npack frame failed %d\n", ret);
  1407. ret = -1;
  1408. goto leave;
  1409. }
  1410. // dlt645api_show_packet(length, buffer);
  1411. for (i = 0; i < length; i++)
  1412. {
  1413. e[i].c = buffer[i];
  1414. // log_dbg("%02X ", buffer[i]);
  1415. }
  1416. // chan_lock(dev->comm.chanidx);
  1417. chan_serial_rxrb_init(dev->comm.chanidx);
  1418. chan_serial_txrb_init(dev->comm.chanidx);
  1419. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  1420. dev->recvst = MRECV_WAIT4STX;
  1421. cnt = DELAY_CNT;
  1422. while (cnt-- > 0)
  1423. {
  1424. usleep(10000); /* 10ms */
  1425. rc = dlt645_recv_rsp(idx);
  1426. if (rc == 0)
  1427. {
  1428. break;
  1429. }
  1430. }
  1431. // chan_unlock(dev->comm.chanidx);
  1432. if (rc == 0)
  1433. {
  1434. // log_dbg("frame is : ");
  1435. // for(i = 0; i < dev->recvcnt; i++){
  1436. // log_dbg("%02X ",dev->recvbuf[i]);
  1437. // }
  1438. // dlt645api_debug_switch(D07_ON);
  1439. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  1440. // dlt645api_debug_switch(D07_OFF);
  1441. if (ret != E_D07_OK)
  1442. {
  1443. log_dbg("\n error! (error = %d : ", ret);
  1444. switch (ret)
  1445. {
  1446. case E_D07_ERRO_FRAME_UNCOMP:
  1447. log_dbg("frame not complete)\n");
  1448. break;
  1449. case E_D07_ERRO_FRAME_0x68:
  1450. log_dbg("start 0x68 position err)\n");
  1451. break;
  1452. case E_D07_ERRO_FRAME_CHECK_SUM:
  1453. log_dbg("chksum error)\n");
  1454. break;
  1455. case E_D07_ERRO_FRAME_END_0x16:
  1456. log_dbg("end 0x16 err)\n");
  1457. break;
  1458. default:
  1459. break;
  1460. }
  1461. ret = -1;
  1462. goto leave;
  1463. }
  1464. if (stUnPack.ruler_id != E_D07_RULER_TYPE_FORTH_HAVE_POWER_TOTAL)
  1465. {
  1466. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  1467. ret = -1;
  1468. goto leave;
  1469. }
  1470. else
  1471. {
  1472. dev->pos_active_e = stUnPack.data_unpack.fPower * dev->pratio;
  1473. // log_dbg("%s, pos_ae = %.2f", __func__, dev->pos_active_e);
  1474. ret = 0;
  1475. goto leave;
  1476. }
  1477. }
  1478. else
  1479. {
  1480. ret = -1;
  1481. goto leave;
  1482. }
  1483. leave:
  1484. if (ret < 0)
  1485. {
  1486. log_dbg("%s, --, ret:%d", __func__, ret);
  1487. }
  1488. return ret;
  1489. }
  1490. int dlt645_read_neg_ae(int idx)
  1491. {
  1492. int num = 1;
  1493. struct dlt645_t *dev = &dlt645[idx];
  1494. char addr[64] = {0};
  1495. unsigned long inRulerID;
  1496. S_D07_RULER_INFO info = {0};
  1497. F_D07_RULER_TRANS func = NULL;
  1498. S_D07_PACK_FRAME pack_frame = {0};
  1499. S_D07_UNPACK stUnPack = {0};
  1500. unsigned char ucCtrl = 0;
  1501. int length = 0;
  1502. char buffer[256] = {0};
  1503. int ret, i, cnt, rc;
  1504. chan_serial_ringbuffer_element_t e[256];
  1505. // log_dbg("%s, ++", __func__);
  1506. inRulerID = E_D07_RULER_TYPE_BACK_HAVE_POWER_TOTAL;
  1507. ret = get_d07_ruler_info(inRulerID, &info);
  1508. S_D07_CTRL_CODE stCtrl = {0};
  1509. strcpy(addr, dev->szaddr);
  1510. stCtrl.direct = E_D07_CTRL_DIR_M2S;
  1511. stCtrl.funcode = E_D07_CTRL_READ_DATA;
  1512. pack_frame.data_len = 4;
  1513. pack_frame.data = NULL;
  1514. ret = trans_d07ctrl_struct2char(&ucCtrl, &stCtrl);
  1515. if (ret != E_D07_OK)
  1516. {
  1517. log_dbg("\ntrans_d07ctrl_struct2char failed %d\n", ret);
  1518. ret = -1;
  1519. goto leave;
  1520. }
  1521. pack_frame.ruler_id = inRulerID;
  1522. pack_frame.ctrl_code = ucCtrl;
  1523. memcpy(pack_frame.address, addr, 13);
  1524. ret = pack_d07_frame_by_data(&pack_frame, buffer, &length);
  1525. if (ret != E_D07_OK)
  1526. {
  1527. log_dbg("\npack frame failed %d\n", ret);
  1528. ret = -1;
  1529. goto leave;
  1530. }
  1531. // dlt645api_show_packet(length, buffer);
  1532. for (i = 0; i < length; i++)
  1533. {
  1534. e[i].c = buffer[i];
  1535. // log_dbg("%02X ", buffer[i]);
  1536. }
  1537. // chan_lock(dev->comm.chanidx);
  1538. chan_serial_rxrb_init(dev->comm.chanidx);
  1539. chan_serial_txrb_init(dev->comm.chanidx);
  1540. chan_serial_txrb_queue_arr(dev->comm.chanidx, e, length);
  1541. dev->recvst = MRECV_WAIT4STX;
  1542. cnt = DELAY_CNT;
  1543. while (cnt-- > 0)
  1544. {
  1545. usleep(10000); /* 10ms */
  1546. rc = dlt645_recv_rsp(idx);
  1547. if (rc == 0)
  1548. {
  1549. break;
  1550. }
  1551. }
  1552. // chan_unlock(dev->comm.chanidx);
  1553. if (rc == 0)
  1554. {
  1555. // log_dbg("frame is : ");
  1556. // for(i = 0; i < dev->recvcnt; i++){
  1557. // log_dbg("%02X ",dev->recvbuf[i]);
  1558. // }
  1559. // dlt645api_debug_switch(D07_ON);
  1560. rc = dlt645api_unpack_d07_frame(dev->recvbuf, dev->recvcnt, &stUnPack);
  1561. // dlt645api_debug_switch(D07_OFF);
  1562. if (ret != E_D07_OK)
  1563. {
  1564. log_dbg("\n error! (error = %d : ", ret);
  1565. switch (ret)
  1566. {
  1567. case E_D07_ERRO_FRAME_UNCOMP:
  1568. log_dbg("frame not complete)\n");
  1569. break;
  1570. case E_D07_ERRO_FRAME_0x68:
  1571. log_dbg("start 0x68 position err)\n");
  1572. break;
  1573. case E_D07_ERRO_FRAME_CHECK_SUM:
  1574. log_dbg("chksum error)\n");
  1575. break;
  1576. case E_D07_ERRO_FRAME_END_0x16:
  1577. log_dbg("end 0x16 err)\n");
  1578. break;
  1579. default:
  1580. break;
  1581. }
  1582. ret = -1;
  1583. goto leave;
  1584. }
  1585. if (stUnPack.ruler_id != E_D07_RULER_TYPE_BACK_HAVE_POWER_TOTAL)
  1586. {
  1587. log_dbg("%s, stUnPack.ruler_id not correct ", __func__);
  1588. ret = -1;
  1589. goto leave;
  1590. }
  1591. else
  1592. {
  1593. dev->neg_active_e = stUnPack.data_unpack.fPower * dev->pratio;
  1594. // log_dbg("%s, neg_ae = %.2f", __func__, dev->neg_active_e);
  1595. ret = 0;
  1596. goto leave;
  1597. }
  1598. }
  1599. else
  1600. {
  1601. ret = -1;
  1602. goto leave;
  1603. }
  1604. leave:
  1605. if (ret < 0)
  1606. {
  1607. log_dbg("%s, --, ret:%d", __func__, ret);
  1608. }
  1609. return ret;
  1610. }
  1611. #if 0
  1612. void dlt645_comm_dac(int idx)
  1613. {
  1614. struct dlt645_t* dev = &dlt645[idx];
  1615. struct comm_t* comm = &dev->comm;
  1616. int trycnt;
  1617. if(comm_get_state(comm) != COMMST_NORMAL){
  1618. return;
  1619. }
  1620. comm_start_cal_dac_timing(comm);
  1621. trycnt = 0;
  1622. while( 1 ){
  1623. if( dlt645_read_com_ap(idx) == 0){
  1624. break;
  1625. }else{
  1626. if( trycnt++ >= 3 ){
  1627. comm_set_state(comm, COMMST_ERR);
  1628. return;
  1629. }else{
  1630. usleep(100000); /* 100ms */
  1631. }
  1632. }
  1633. }
  1634. usleep(100000); /* 100ms */
  1635. if( dev->comm.dac.stp == 0 ){ /* com_ae */
  1636. trycnt = 0;
  1637. while( 1 ){
  1638. if( dlt645_read_com_ae(idx) == 0){
  1639. break;
  1640. }else{
  1641. if( trycnt++ >= 3 ){
  1642. comm_set_state(comm, COMMST_ERR);
  1643. return;
  1644. }else{
  1645. usleep(100000); /* 100ms */
  1646. }
  1647. }
  1648. }
  1649. usleep(100000); /* 100ms */
  1650. dev->comm.dac.stp = 1;
  1651. }else if( dev->comm.dac.stp == 1 ){
  1652. trycnt = 0;
  1653. while( 1 ){
  1654. if( dlt645_read_pos_ae(idx) == 0){
  1655. break;
  1656. }else{
  1657. if( trycnt++ >= 3 ){
  1658. comm_set_state(comm, COMMST_ERR);
  1659. return;
  1660. }else{
  1661. usleep(100000); /* 100ms */
  1662. }
  1663. }
  1664. }
  1665. usleep(100000); /* 100ms */
  1666. dev->comm.dac.stp = 2;
  1667. }else if( dev->comm.dac.stp == 2 ){
  1668. trycnt = 0;
  1669. while( 1 ){
  1670. if( dlt645_read_neg_ae(idx) == 0){
  1671. break;
  1672. }else{
  1673. if( trycnt++ >= 3 ){
  1674. comm_set_state(comm, COMMST_ERR);
  1675. return;
  1676. }else{
  1677. usleep(100000); /* 100ms */
  1678. }
  1679. }
  1680. }
  1681. usleep(100000); /* 100ms */
  1682. dev->comm.dac.stp = 3;
  1683. }else if( dev->comm.dac.stp == 3 ){
  1684. trycnt = 0;
  1685. while( 1 ){
  1686. if( dlt645_read_ua(idx) == 0){
  1687. break;
  1688. }else{
  1689. if( trycnt++ >= 3 ){
  1690. comm_set_state(comm, COMMST_ERR);
  1691. return;
  1692. }else{
  1693. usleep(100000); /* 100ms */
  1694. }
  1695. }
  1696. }
  1697. usleep(100000); /* 100ms */
  1698. dev->comm.dac.stp = 4;
  1699. }else if( dev->comm.dac.stp == 4 ){
  1700. trycnt = 0;
  1701. while( 1 ){
  1702. if( dlt645_read_ub(idx) == 0){
  1703. break;
  1704. }else{
  1705. if( trycnt++ >= 3 ){
  1706. comm_set_state(comm, COMMST_ERR);
  1707. return;
  1708. }else{
  1709. usleep(100000); /* 100ms */
  1710. }
  1711. }
  1712. }
  1713. usleep(100000); /* 100ms */
  1714. dev->comm.dac.stp = 5;
  1715. }else if( dev->comm.dac.stp == 5 ){
  1716. trycnt = 0;
  1717. while( 1 ){
  1718. if( dlt645_read_uc(idx) == 0){
  1719. break;
  1720. }else{
  1721. if( trycnt++ >= 3 ){
  1722. comm_set_state(comm, COMMST_ERR);
  1723. return;
  1724. }else{
  1725. usleep(100000); /* 100ms */
  1726. }
  1727. }
  1728. }
  1729. usleep(100000); /* 100ms */
  1730. dev->comm.dac.stp = 6;
  1731. }else if( dev->comm.dac.stp == 6 ){
  1732. trycnt = 0;
  1733. while( 1 ){
  1734. if( dlt645_read_ia(idx) == 0){
  1735. break;
  1736. }else{
  1737. if( trycnt++ >= 3 ){
  1738. comm_set_state(comm, COMMST_ERR);
  1739. return;
  1740. }else{
  1741. usleep(100000); /* 100ms */
  1742. }
  1743. }
  1744. }
  1745. usleep(100000); /* 100ms */
  1746. dev->comm.dac.stp = 7;
  1747. }else if( dev->comm.dac.stp == 7 ){
  1748. trycnt = 0;
  1749. while( 1 ){
  1750. if( dlt645_read_ib(idx) == 0){
  1751. break;
  1752. }else{
  1753. if( trycnt++ >= 3 ){
  1754. comm_set_state(comm, COMMST_ERR);
  1755. return;
  1756. }else{
  1757. usleep(100000); /* 100ms */
  1758. }
  1759. }
  1760. }
  1761. usleep(100000); /* 100ms */
  1762. dev->comm.dac.stp = 8;
  1763. }else if( dev->comm.dac.stp == 8 ){ /* ic */
  1764. trycnt = 0;
  1765. while( 1 ){
  1766. if( dlt645_read_ic(idx) == 0){
  1767. break;
  1768. }else{
  1769. if( trycnt++ >= 3 ){
  1770. comm_set_state(comm, COMMST_ERR);
  1771. return;
  1772. }else{
  1773. usleep(100000); /* 100ms */
  1774. }
  1775. }
  1776. }
  1777. usleep(100000); /* 100ms */
  1778. dev->comm.dac.stp = 0;
  1779. comm_stop_cal_dac_timing(comm);
  1780. }else{
  1781. dev->comm.dac.stp = 0;
  1782. }
  1783. }
  1784. #endif
  1785. void dlt645_comm_dac(int idx)
  1786. {
  1787. struct dlt645_t *dev = &dlt645[idx];
  1788. struct comm_t *comm = &dev->comm;
  1789. int trycnt;
  1790. if (comm_get_state(comm) != COMMST_NORMAL)
  1791. {
  1792. return;
  1793. }
  1794. comm_start_cal_dac_timing(comm);
  1795. trycnt = 0;
  1796. while (1)
  1797. {
  1798. if (dlt645_read_com_ap(idx) == 0)
  1799. {
  1800. break;
  1801. }
  1802. else
  1803. {
  1804. if (trycnt++ >= 3)
  1805. {
  1806. comm_set_state(comm, COMMST_ERR);
  1807. return;
  1808. }
  1809. else
  1810. {
  1811. usleep(100000); /* 100ms */
  1812. }
  1813. }
  1814. }
  1815. usleep(100000); /* 100ms */
  1816. trycnt = 0;
  1817. while (1)
  1818. {
  1819. if (dlt645_read_com_ae(idx) == 0)
  1820. {
  1821. break;
  1822. }
  1823. else
  1824. {
  1825. if (trycnt++ >= 3)
  1826. {
  1827. comm_set_state(comm, COMMST_ERR);
  1828. return;
  1829. }
  1830. else
  1831. {
  1832. usleep(100000); /* 100ms */
  1833. }
  1834. }
  1835. }
  1836. usleep(100000); /* 100ms */
  1837. trycnt = 0;
  1838. while (1)
  1839. {
  1840. if (dlt645_read_pos_ae(idx) == 0)
  1841. {
  1842. break;
  1843. }
  1844. else
  1845. {
  1846. if (trycnt++ >= 3)
  1847. {
  1848. comm_set_state(comm, COMMST_ERR);
  1849. return;
  1850. }
  1851. else
  1852. {
  1853. usleep(100000); /* 100ms */
  1854. }
  1855. }
  1856. }
  1857. usleep(100000); /* 100ms */
  1858. trycnt = 0;
  1859. while (1)
  1860. {
  1861. if (dlt645_read_neg_ae(idx) == 0)
  1862. {
  1863. break;
  1864. }
  1865. else
  1866. {
  1867. if (trycnt++ >= 3)
  1868. {
  1869. comm_set_state(comm, COMMST_ERR);
  1870. return;
  1871. }
  1872. else
  1873. {
  1874. usleep(100000); /* 100ms */
  1875. }
  1876. }
  1877. }
  1878. usleep(100000); /* 100ms */
  1879. if (dev->comm.dac.stp == 0)
  1880. {
  1881. trycnt = 0;
  1882. while (1)
  1883. {
  1884. if (dlt645_read_ua(idx) == 0)
  1885. {
  1886. break;
  1887. }
  1888. else
  1889. {
  1890. if (trycnt++ >= 3)
  1891. {
  1892. comm_set_state(comm, COMMST_ERR);
  1893. return;
  1894. }
  1895. else
  1896. {
  1897. usleep(100000); /* 100ms */
  1898. }
  1899. }
  1900. }
  1901. usleep(100000); /* 100ms */
  1902. dev->comm.dac.stp = 1;
  1903. }
  1904. else if (dev->comm.dac.stp == 1)
  1905. {
  1906. trycnt = 0;
  1907. while (1)
  1908. {
  1909. if (dlt645_read_ub(idx) == 0)
  1910. {
  1911. break;
  1912. }
  1913. else
  1914. {
  1915. if (trycnt++ >= 3)
  1916. {
  1917. comm_set_state(comm, COMMST_ERR);
  1918. return;
  1919. }
  1920. else
  1921. {
  1922. usleep(100000); /* 100ms */
  1923. }
  1924. }
  1925. }
  1926. usleep(100000); /* 100ms */
  1927. dev->comm.dac.stp = 2;
  1928. }
  1929. else if (dev->comm.dac.stp == 2)
  1930. {
  1931. trycnt = 0;
  1932. while (1)
  1933. {
  1934. if (dlt645_read_uc(idx) == 0)
  1935. {
  1936. break;
  1937. }
  1938. else
  1939. {
  1940. if (trycnt++ >= 3)
  1941. {
  1942. comm_set_state(comm, COMMST_ERR);
  1943. return;
  1944. }
  1945. else
  1946. {
  1947. usleep(100000); /* 100ms */
  1948. }
  1949. }
  1950. }
  1951. usleep(100000); /* 100ms */
  1952. dev->comm.dac.stp = 3;
  1953. }
  1954. else if (dev->comm.dac.stp == 3)
  1955. {
  1956. trycnt = 0;
  1957. while (1)
  1958. {
  1959. if (dlt645_read_ia(idx) == 0)
  1960. {
  1961. break;
  1962. }
  1963. else
  1964. {
  1965. if (trycnt++ >= 3)
  1966. {
  1967. comm_set_state(comm, COMMST_ERR);
  1968. return;
  1969. }
  1970. else
  1971. {
  1972. usleep(100000); /* 100ms */
  1973. }
  1974. }
  1975. }
  1976. usleep(100000); /* 100ms */
  1977. dev->comm.dac.stp = 4;
  1978. }
  1979. else if (dev->comm.dac.stp == 4)
  1980. {
  1981. trycnt = 0;
  1982. while (1)
  1983. {
  1984. if (dlt645_read_ib(idx) == 0)
  1985. {
  1986. break;
  1987. }
  1988. else
  1989. {
  1990. if (trycnt++ >= 3)
  1991. {
  1992. comm_set_state(comm, COMMST_ERR);
  1993. return;
  1994. }
  1995. else
  1996. {
  1997. usleep(100000); /* 100ms */
  1998. }
  1999. }
  2000. }
  2001. usleep(100000); /* 100ms */
  2002. dev->comm.dac.stp = 5;
  2003. }
  2004. else if (dev->comm.dac.stp == 5)
  2005. { /* ic */
  2006. trycnt = 0;
  2007. while (1)
  2008. {
  2009. if (dlt645_read_ic(idx) == 0)
  2010. {
  2011. break;
  2012. }
  2013. else
  2014. {
  2015. if (trycnt++ >= 3)
  2016. {
  2017. comm_set_state(comm, COMMST_ERR);
  2018. return;
  2019. }
  2020. else
  2021. {
  2022. usleep(100000); /* 100ms */
  2023. }
  2024. }
  2025. }
  2026. usleep(100000); /* 100ms */
  2027. dev->comm.dac.stp = 0;
  2028. }
  2029. else
  2030. {
  2031. dev->comm.dac.stp = 0;
  2032. }
  2033. comm_stop_cal_dac_timing(comm);
  2034. }
  2035. int dlt645_comm_init(int idx)
  2036. {
  2037. struct dlt645_t *dev = &dlt645[idx];
  2038. struct comm_t *comm = &dev->comm;
  2039. dev->recvst = MRECV_WAIT4STX;
  2040. comm->dac.stp = 0;
  2041. comm_set_state(comm, COMMST_ERR);
  2042. }
  2043. int dlt645_comm_reset(int idx)
  2044. {
  2045. struct dlt645_t *dev = &dlt645[idx];
  2046. struct comm_t *comm = &dev->comm;
  2047. dev->recvst = MRECV_WAIT4STX;
  2048. comm_set_state(comm, COMMST_NORMAL);
  2049. }