n9_comm.c 19 KB

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  1. #include "plt.h"
  2. int n9_comm_init(int idx)
  3. {
  4. struct n9_t *dev = &n9[idx];
  5. struct comm_t *comm = &dev->comm;
  6. comm_set_state(comm, COMMST_ERR);
  7. }
  8. int n9_comm_reset(int idx)
  9. {
  10. struct n9_t *dev = &n9[idx];
  11. struct comm_t *comm = &dev->comm;
  12. comm_set_state(comm, COMMST_NORMAL);
  13. comm_set_dac_param_en(comm, 1);
  14. }
  15. int n9_set_dev_aps(int idx, int aps)
  16. {
  17. int ret = 0;
  18. struct n9_t *dev = &n9[idx];
  19. int chanidx = dev->comm.chanidx;
  20. int addr = dev->comm.adr;
  21. int regaddr = 0x0D57;
  22. int nb = 1;
  23. short val = aps * 10;
  24. // modbus tcp connection, no delay
  25. chan_lock(chanidx);
  26. ret = chan_write_single_register_with_retry(chanidx, addr, regaddr, val);
  27. chan_unlock(chanidx);
  28. if (ret < 0)
  29. {
  30. log_dbg("%s, idx:%d, aps:%d, fail", __func__, idx, aps);
  31. }
  32. else
  33. {
  34. log_dbg("%s, idx:%d, aps:%d, ret:%d", __func__, idx, dev->pow.aps, ret);
  35. }
  36. return ret;
  37. }
  38. int n9_set_dev_startcmd(int idx)
  39. {
  40. int ret = 0;
  41. struct n9_t *dev = &n9[idx];
  42. int chanidx = dev->comm.chanidx;
  43. int addr = dev->comm.adr;
  44. int regaddr = 0x0291;
  45. int nb = 1;
  46. int trycnt = 0;
  47. int val = 1;
  48. // modbus tcp connection, no delay
  49. chan_lock(chanidx);
  50. ret = chan_write_single_register_with_retry(chanidx, addr, regaddr, val);
  51. chan_unlock(chanidx);
  52. if (ret < 0)
  53. {
  54. log_dbg("%s, idx:%d, fail", __func__, idx);
  55. }
  56. return ret;
  57. }
  58. int n9_set_dev_stopcmd(int idx)
  59. {
  60. int ret = 0;
  61. struct n9_t *dev = &n9[idx];
  62. int chanidx = dev->comm.chanidx;
  63. int addr = dev->comm.adr;
  64. int regaddr = 0x0291;
  65. int nb = 1;
  66. int trycnt = 0;
  67. int val = 0;
  68. // modbus tcp connection, no delay
  69. chan_lock(chanidx);
  70. ret = chan_write_single_register_with_retry(chanidx, addr, regaddr, val);
  71. chan_unlock(chanidx);
  72. if (ret < 0)
  73. {
  74. log_dbg("%s, idx:%d, fail", __func__, idx);
  75. }
  76. return ret;
  77. }
  78. // send fault reset cmd to pcs
  79. // 0:invalid 1:reset
  80. int n9_set_dev_resetcmd(int idx)
  81. {
  82. int ret = 0;
  83. struct n9_t *dev = &n9[idx];
  84. int chanidx = dev->comm.chanidx;
  85. int addr = dev->comm.adr;
  86. int regaddr = 0x1400;
  87. int nb = 1;
  88. int trycnt = 0;
  89. unsigned short val = 0;
  90. chan_lock(chanidx);
  91. ret = chan_read_holdingregisters_with_retry(chanidx, addr, regaddr, 1, &val);
  92. chan_unlock(chanidx);
  93. if (ret < 0)
  94. {
  95. log_dbg("%s, idx:%d, read fail", __func__, idx);
  96. return ret;
  97. }
  98. val |= ((unsigned short)1 << 15);
  99. // modbus tcp connection, no delay
  100. chan_lock(chanidx);
  101. ret = chan_write_single_register_with_retry(chanidx, addr, regaddr, val);
  102. chan_unlock(chanidx);
  103. if (ret < 0)
  104. {
  105. log_dbg("%s, idx:%d, fail", __func__, idx);
  106. }
  107. return ret;
  108. }
  109. /*
  110. 1:offgrid
  111. 0:ongrid
  112. **/
  113. int n9_set_dev_runmod(int idx, int val)
  114. {
  115. int ret = 0;
  116. struct n9_t *dev = &n9[idx];
  117. int chanidx = dev->comm.chanidx;
  118. int addr = dev->comm.adr;
  119. int regaddr = 0x5066;
  120. // modbus tcp connection, no delay
  121. chan_lock(chanidx);
  122. ret = chan_write_single_register_with_retry(chanidx, addr, regaddr, val);
  123. chan_unlock(chanidx);
  124. if (ret < 0)
  125. {
  126. log_dbg("%s, idx:%d, fail", __func__, idx);
  127. }
  128. return ret;
  129. }
  130. static void n9_comm_dac_0x6020(int idx)
  131. {
  132. unsigned short tab_us[128] = {0};
  133. struct n9_t *dev = &n9[idx];
  134. struct comm_t *comm = &dev->comm;
  135. int chanidx = dev->comm.chanidx;
  136. int addr = dev->comm.adr;
  137. int start, nb, rc;
  138. if (comm_get_state(comm) != COMMST_NORMAL)
  139. {
  140. return;
  141. }
  142. nb = 14;
  143. start = 0x6020;
  144. chan_lock(chanidx);
  145. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  146. if (rc < 0)
  147. {
  148. comm_set_state(comm, COMMST_ERR);
  149. }
  150. chan_unlock(chanidx);
  151. if (rc == 0)
  152. { /* read ok */
  153. dev->Uab = *((signed short *)(&tab_us[0x6020 - start])) / 10.0;
  154. dev->Ubc = *((signed short *)(&tab_us[0x6021 - start])) / 10.0;
  155. dev->Uca = *((signed short *)(&tab_us[0x6022 - start])) / 10.0;
  156. dev->Ua = *((signed short *)(&tab_us[0x6023 - start])) / 10.0;
  157. dev->Ub = *((signed short *)(&tab_us[0x6024 - start])) / 10.0;
  158. dev->Uc = *((signed short *)(&tab_us[0x6025 - start])) / 10.0;
  159. dev->Ia = *((signed short *)(&tab_us[0x6026 - start])) / 10.0;
  160. dev->Ib = *((signed short *)(&tab_us[0x6027 - start])) / 10.0;
  161. dev->Ic = *((signed short *)(&tab_us[0x6028 - start])) / 10.0;
  162. dev->Ila = *((signed short *)(&tab_us[0x6029 - start])) / 10.0;
  163. dev->Ilb = *((signed short *)(&tab_us[0x602A - start])) / 10.0;
  164. dev->Ilc = *((signed short *)(&tab_us[0x602B - start])) / 10.0;
  165. dev->gridf = *((signed short *)(&tab_us[0x602C - start])) / 100.0;
  166. dev->phase = *((signed short *)(&tab_us[0x602D - start]));
  167. }
  168. }
  169. static void n9_comm_dac_0x6030(int idx)
  170. {
  171. unsigned short tab_us[256] = {0};
  172. struct n9_t *dev = &n9[idx];
  173. struct comm_t *comm = &dev->comm;
  174. int chanidx = dev->comm.chanidx;
  175. int addr = dev->comm.adr;
  176. int start, nb, rc;
  177. if (comm_get_state(comm) != COMMST_NORMAL)
  178. {
  179. return;
  180. }
  181. nb = 13;
  182. start = 0x6030;
  183. chan_lock(chanidx);
  184. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  185. if (rc < 0)
  186. {
  187. comm_set_state(comm, COMMST_ERR);
  188. }
  189. chan_unlock(chanidx);
  190. if (rc == 0)
  191. { /* read ok */
  192. dev->Pa = *((signed short *)(&tab_us[0x6030 - start])) / 10.0;
  193. dev->Pb = *((signed short *)(&tab_us[0x6031 - start])) / 10.0;
  194. dev->Pc = *((signed short *)(&tab_us[0x6032 - start])) / 10.0;
  195. dev->Sa = *((signed short *)(&tab_us[0x6033 - start])) / 10.0;
  196. dev->Sb = *((signed short *)(&tab_us[0x6034 - start])) / 10.0;
  197. dev->Sc = *((signed short *)(&tab_us[0x6035 - start])) / 10.0;
  198. dev->Qa = *((signed short *)(&tab_us[0x6036 - start])) / 10.0;
  199. dev->Qb = *((signed short *)(&tab_us[0x6037 - start])) / 10.0;
  200. dev->Qc = *((signed short *)(&tab_us[0x6038 - start])) / 10.0;
  201. dev->ap = *((signed short *)(&tab_us[0x6039 - start])) / 10.0;
  202. dev->Ssum = *((signed short *)(&tab_us[0x603A - start])) / 10.0;
  203. dev->Qsum = *((signed short *)(&tab_us[0x603B - start])) / 10.0;
  204. dev->Pfactor = *((signed short *)(&tab_us[0x603C - start])) / 100.0;
  205. static double ap_old = 0.0;
  206. if (fabs(ap_old - dev->ap) > 1e-5)
  207. {
  208. ap_old = dev->ap;
  209. log_info("%s, dev ap now : (%.1f)", __func__, dev->ap);
  210. }
  211. }
  212. }
  213. static void n9_comm_dac_0x6050(int idx)
  214. {
  215. unsigned short tab_us[128] = {0};
  216. struct n9_t *dev = &n9[idx];
  217. struct comm_t *comm = &dev->comm;
  218. int chanidx = dev->comm.chanidx;
  219. int addr = dev->comm.adr;
  220. int start, nb, rc;
  221. if (comm_get_state(comm) != COMMST_NORMAL)
  222. {
  223. return;
  224. }
  225. nb = 12;
  226. start = 0x6050;
  227. chan_lock(chanidx);
  228. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  229. if (rc < 0)
  230. {
  231. comm_set_state(comm, COMMST_ERR);
  232. }
  233. chan_unlock(chanidx);
  234. if (rc == 0)
  235. { /* read ok */
  236. dev->dc_v = *((signed short *)(&tab_us[0x6050 - start])) / 10.0;
  237. dev->dc_v_pos = *((signed short *)(&tab_us[0x6051 - start])) / 10.0;
  238. dev->dc_v_neg = *((signed short *)(&tab_us[0x6052 - start])) / 10.0;
  239. dev->bat_v = *((signed short *)(&tab_us[0x6053 - start])) / 10.0;
  240. dev->bat_c = *((signed short *)(&tab_us[0x6054 - start])) / 10.0;
  241. dev->dc_ap = *((signed short *)(&tab_us[0x6055 - start])) / 10.0;
  242. dev->dc_c = *((signed short *)(&tab_us[0x6056 - start])) / 10.0;
  243. dev->workmode = tab_us[0x6057 - start];
  244. if ((dev->workmode & (unsigned short)1 << 0))
  245. {
  246. dev->runstate = N9_RUNSTAT_RUN;
  247. if ((dev->workmode & (unsigned short)1 << 3))
  248. {
  249. dev->cv = 1;
  250. }
  251. else
  252. {
  253. dev->cv = 0;
  254. }
  255. if ((dev->workmode & (unsigned short)1 << 8))
  256. {
  257. dev->cc = 1;
  258. }
  259. else
  260. {
  261. dev->cc = 0;
  262. }
  263. strcpy(dev->runstate_str, "run");
  264. }
  265. else if (dev->workmode & (1 << 6))
  266. {
  267. dev->runstate = N9_RUNSTAT_ERROR;
  268. strcpy(dev->runstate_str, "error, check faults");
  269. }
  270. else
  271. {
  272. dev->runstate = N9_RUNSTAT_IDLE;
  273. strcpy(dev->runstate_str, "idle");
  274. }
  275. dev->t_igbt = tab_us[0x6058 - start] / 10.0;
  276. dev->t_env = *((signed short *)(&tab_us[0x6059 - start])) / 10.0;
  277. dev->c_dhg_mode = tab_us[0x605B - start];
  278. if (dev->c_dhg_mode == 0)
  279. {
  280. strcpy(dev->c_dhg_mode_str, "bat constant voltage");
  281. }
  282. else if (dev->c_dhg_mode == 1)
  283. {
  284. strcpy(dev->c_dhg_mode_str, "ongrid constant current");
  285. }
  286. else if (dev->c_dhg_mode == 2)
  287. {
  288. strcpy(dev->c_dhg_mode_str, "bat constant current");
  289. }
  290. }
  291. }
  292. static void n9_comm_dac_0x0D57(int idx)
  293. {
  294. unsigned short tab_us[256] = {0};
  295. struct n9_t *dev = &n9[idx];
  296. struct comm_t *comm = &dev->comm;
  297. int chanidx = dev->comm.chanidx;
  298. int addr = dev->comm.adr;
  299. int start, nb, rc;
  300. if (comm_get_state(comm) != COMMST_NORMAL)
  301. {
  302. return;
  303. }
  304. nb = 2;
  305. start = 0x0D57;
  306. chan_lock(chanidx);
  307. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  308. if (rc < 0)
  309. {
  310. comm_set_state(comm, COMMST_ERR);
  311. }
  312. chan_unlock(chanidx);
  313. if (rc == 0)
  314. { /* read ok */
  315. dev->Pset = *((signed short *)(&tab_us[0x0D57 - start])) / 10.0;
  316. }
  317. }
  318. // 0x0E14 fault state word
  319. static void n9_comm_dac_0x6000(int idx)
  320. {
  321. unsigned short tab_us[128] = {0};
  322. struct n9_t *dev = &n9[idx];
  323. struct comm_t *comm = &dev->comm;
  324. int chanidx = dev->comm.chanidx;
  325. int addr = dev->comm.adr;
  326. int start, nb, rc;
  327. if (comm_get_state(comm) != COMMST_NORMAL)
  328. {
  329. return;
  330. }
  331. nb = 6;
  332. start = 0x6000;
  333. chan_lock(chanidx);
  334. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  335. if (rc < 0)
  336. {
  337. comm_set_state(comm, COMMST_ERR);
  338. }
  339. chan_unlock(chanidx);
  340. if (rc == 0)
  341. { /* read ok */
  342. dev->dsp_ver[0] = tab_us[0x6000 - start];
  343. dev->dsp_ver[1] = tab_us[0x6001 - start];
  344. dev->dsp_ver[2] = tab_us[0x6002 - start];
  345. dev->cpld_ver[0] = tab_us[0x6003 - start];
  346. dev->cpld_ver[1] = tab_us[0x6004 - start];
  347. dev->cpld_ver[2] = tab_us[0x6005 - start];
  348. }
  349. }
  350. static void n9_comm_dac_0x6010(int idx)
  351. {
  352. unsigned short tab_us[128] = {0};
  353. struct n9_t *dev = &n9[idx];
  354. struct comm_t *comm = &dev->comm;
  355. int chanidx = dev->comm.chanidx;
  356. int addr = dev->comm.adr;
  357. int start, nb, rc;
  358. unsigned int temp = 0;
  359. if (comm_get_state(comm) != COMMST_NORMAL)
  360. {
  361. return;
  362. }
  363. nb = 16;
  364. start = 0x6010;
  365. chan_lock(chanidx);
  366. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  367. if (rc < 0)
  368. {
  369. comm_set_state(comm, COMMST_ERR);
  370. }
  371. chan_unlock(chanidx);
  372. if (rc == 0)
  373. { /* read ok */
  374. temp = tab_us[0x6010 - start];
  375. temp = (temp << 16) + tab_us[0x6011 - start];
  376. dev->chg_power_total_dc = temp;
  377. temp = tab_us[0x6012 - start];
  378. temp = (temp << 16) + tab_us[0x6013 - start];
  379. dev->chg_power_day_sum_dc = temp;
  380. temp = tab_us[0x6014 - start];
  381. temp = (temp << 16) + tab_us[0x6015 - start];
  382. dev->dhg_power_total_dc = temp;
  383. temp = tab_us[0x6016 - start];
  384. temp = (temp << 16) + tab_us[0x6017 - start];
  385. dev->dhg_power_day_sum_dc = temp;
  386. temp = tab_us[0x6018 - start];
  387. temp = (temp << 16) + tab_us[0x6019 - start];
  388. dev->chg_power_total_ac = temp;
  389. temp = tab_us[0x601A - start];
  390. temp = (temp << 16) + tab_us[0x601B - start];
  391. dev->chg_power_day_sum_ac = temp;
  392. temp = tab_us[0x601C - start];
  393. temp = (temp << 16) + tab_us[0x601D - start];
  394. dev->dhg_power_total_ac = temp;
  395. temp = tab_us[0x601E - start];
  396. temp = (temp << 16) + tab_us[0x601F - start];
  397. dev->dhg_power_day_sum_ac = temp;
  398. // log_info("%s,buf[%d,%d],sum:%d",__func__,tab_us[0x601C - start],tab_us[0x601D - start],dev->dhg_power_sum_ac);
  399. }
  400. }
  401. static void n9_comm_dac_0x1700(int idx)
  402. {
  403. unsigned short tab_us[128] = {0};
  404. struct n9_t *dev = &n9[idx];
  405. struct comm_t *comm = &dev->comm;
  406. int chanidx = dev->comm.chanidx;
  407. int addr = dev->comm.adr;
  408. int start, nb, rc;
  409. if (comm_get_state(comm) != COMMST_NORMAL)
  410. {
  411. return;
  412. }
  413. nb = 8;
  414. start = 0x1700;
  415. chan_lock(chanidx);
  416. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  417. if (rc < 0)
  418. {
  419. comm_set_state(comm, COMMST_ERR);
  420. }
  421. chan_unlock(chanidx);
  422. if (rc == 0)
  423. { /* read ok */
  424. dev->faults[0] = tab_us[0x1700 - start];
  425. dev->faults[1] = tab_us[0x1701 - start];
  426. dev->faults[2] = tab_us[0x1702 - start];
  427. dev->faults[3] = tab_us[0x1703 - start];
  428. dev->faults[4] = tab_us[0x1704 - start];
  429. dev->faults[5] = tab_us[0x1705 - start];
  430. dev->faults[6] = tab_us[0x1706 - start];
  431. dev->faults[7] = tab_us[0x1707 - start];
  432. static unsigned short faults[8] = {0};
  433. if (dev->faults[0] != faults[0])
  434. {
  435. faults[0] = dev->faults[0];
  436. log_dbg("faults[0]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[0]));
  437. }
  438. if (dev->faults[1] != faults[1])
  439. {
  440. faults[1] = dev->faults[1];
  441. log_dbg("faults[1]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[1]));
  442. }
  443. if (dev->faults[2] != faults[2])
  444. {
  445. faults[2] = dev->faults[2];
  446. log_dbg("faults[2]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[2]));
  447. }
  448. if (dev->faults[3] != faults[3])
  449. {
  450. faults[3] = dev->faults[3];
  451. log_dbg("faults[3]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[3]));
  452. }
  453. if (dev->faults[4] != faults[4])
  454. {
  455. faults[4] = dev->faults[4];
  456. log_dbg("faults[4]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[4]));
  457. }
  458. if (dev->faults[5] != faults[5])
  459. {
  460. faults[5] = dev->faults[5];
  461. log_dbg("faults[5]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[5]));
  462. }
  463. if (dev->faults[6] != faults[6])
  464. {
  465. faults[6] = dev->faults[6];
  466. log_dbg("faults[6]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[6]));
  467. }
  468. if (dev->faults[7] != faults[7])
  469. {
  470. faults[7] = dev->faults[7];
  471. log_dbg("faults[7]: " BYTE_TO_BINARY_PATTERN, BYTE_TO_BINARY(dev->faults[7]));
  472. }
  473. }
  474. }
  475. static void n9_comm_dac_0x1600(int idx)
  476. {
  477. unsigned short tab_us[128] = {0};
  478. struct n9_t *dev = &n9[idx];
  479. struct comm_t *comm = &dev->comm;
  480. int chanidx = dev->comm.chanidx;
  481. int addr = dev->comm.adr;
  482. int start, nb, rc;
  483. if (comm_get_state(comm) != COMMST_NORMAL)
  484. {
  485. return;
  486. }
  487. nb = 4;
  488. start = 0x1600;
  489. chan_lock(chanidx);
  490. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  491. if (rc < 0)
  492. {
  493. comm_set_state(comm, COMMST_ERR);
  494. }
  495. chan_unlock(chanidx);
  496. if (rc == 0)
  497. { /* read ok */
  498. dev->AC_ovp = tab_us[0x1600 - start] / 10.0;
  499. dev->AC_uvp = tab_us[0x1601 - start] / 10.0;
  500. dev->AC_ocp = tab_us[0x1603 - start] / 10.0;
  501. }
  502. }
  503. static void n9_comm_dac_0x1611(int idx)
  504. {
  505. unsigned short tab_us[128] = {0};
  506. struct n9_t *dev = &n9[idx];
  507. struct comm_t *comm = &dev->comm;
  508. int chanidx = dev->comm.chanidx;
  509. int addr = dev->comm.adr;
  510. int start, nb, rc;
  511. if (comm_get_state(comm) != COMMST_NORMAL)
  512. {
  513. return;
  514. }
  515. nb = 2;
  516. start = 0x1611;
  517. chan_lock(chanidx);
  518. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  519. if (rc < 0)
  520. {
  521. comm_set_state(comm, COMMST_ERR);
  522. }
  523. chan_unlock(chanidx);
  524. if (rc == 0)
  525. { /* read ok */
  526. dev->Ubus_ovp = tab_us[0x1611 - start] / 10.0;
  527. dev->Ubus_uvp = tab_us[0x1612 - start] / 10.0;
  528. }
  529. }
  530. static void n9_comm_dac_0x1620(int idx)
  531. {
  532. unsigned short tab_us[128] = {0};
  533. struct n9_t *dev = &n9[idx];
  534. struct comm_t *comm = &dev->comm;
  535. int chanidx = dev->comm.chanidx;
  536. int addr = dev->comm.adr;
  537. int start, nb, rc;
  538. if (comm_get_state(comm) != COMMST_NORMAL)
  539. {
  540. return;
  541. }
  542. nb = 1;
  543. start = 0x1620;
  544. chan_lock(chanidx);
  545. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  546. if (rc < 0)
  547. {
  548. comm_set_state(comm, COMMST_ERR);
  549. }
  550. chan_unlock(chanidx);
  551. if (rc == 0)
  552. { /* read ok */
  553. dev->module_otp = tab_us[0x1620 - start] / 10.0;
  554. }
  555. }
  556. static void n9_comm_dac_0x1640(int idx)
  557. {
  558. unsigned short tab_us[128] = {0};
  559. struct n9_t *dev = &n9[idx];
  560. struct comm_t *comm = &dev->comm;
  561. int chanidx = dev->comm.chanidx;
  562. int addr = dev->comm.adr;
  563. int start, nb, rc;
  564. if (comm_get_state(comm) != COMMST_NORMAL)
  565. {
  566. return;
  567. }
  568. nb = 1;
  569. start = 0x1640;
  570. chan_lock(chanidx);
  571. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  572. if (rc < 0)
  573. {
  574. comm_set_state(comm, COMMST_ERR);
  575. }
  576. chan_unlock(chanidx);
  577. if (rc == 0)
  578. { /* read ok */
  579. dev->Ubus_ocp = tab_us[0x1640 - start] / 10.0;
  580. }
  581. }
  582. static void n9_comm_dac_0x1633(int idx)
  583. {
  584. unsigned short tab_us[128] = {0};
  585. struct n9_t *dev = &n9[idx];
  586. struct comm_t *comm = &dev->comm;
  587. int chanidx = dev->comm.chanidx;
  588. int addr = dev->comm.adr;
  589. int start, nb, rc;
  590. if (comm_get_state(comm) != COMMST_NORMAL)
  591. {
  592. return;
  593. }
  594. nb = 2;
  595. start = 0x1633;
  596. chan_lock(chanidx);
  597. rc = chan_read_holdingregisters_with_retry(chanidx, addr, start, nb, tab_us);
  598. if (rc < 0)
  599. {
  600. comm_set_state(comm, COMMST_ERR);
  601. }
  602. chan_unlock(chanidx);
  603. if (rc == 0)
  604. { /* read ok */
  605. dev->bat_ovp = tab_us[0x1633 - start] / 10.0;
  606. dev->bat_uvp = tab_us[0x1634 - start] / 10.0;
  607. }
  608. }
  609. void n9_comm_dac(int idx)
  610. {
  611. struct n9_t *dev = &n9[idx];
  612. struct comm_t *comm = &dev->comm;
  613. unsigned short tab_us[128] = {0};
  614. int start, nb;
  615. int chan_idx = dev->comm.chanidx;
  616. int addr = dev->comm.adr;
  617. int ret = 0;
  618. static int cnt = 0;
  619. if (comm_get_state(comm) != COMMST_NORMAL)
  620. {
  621. return;
  622. }
  623. comm_start_cal_dac_timing(comm);
  624. if (sm_get_state(&dev->sm) == SMST_READY && sm_get_step(&dev->sm) == 0)
  625. {
  626. log_dbg("%s, idx:%d, about to enter ready state, stop dac", __func__, idx);
  627. return;
  628. }
  629. if (comm_get_dac_param_en(comm) == 1)
  630. {
  631. comm_set_dac_param_en(comm, 0);
  632. n9_comm_dac_0x1600(idx);
  633. n9_comm_dac_0x1611(idx);
  634. n9_comm_dac_0x1620(idx);
  635. n9_comm_dac_0x1633(idx);
  636. n9_comm_dac_0x1640(idx);
  637. n9_comm_dac_0x6000(idx);
  638. // read protect params
  639. }
  640. if (++cnt > 10)
  641. {
  642. n9_comm_dac_0x6010(idx);
  643. cnt = 0;
  644. }
  645. n9_comm_dac_0x6020(idx);
  646. n9_comm_dac_0x6030(idx);
  647. n9_comm_dac_0x6050(idx);
  648. // n9_comm_dac_0x6000(idx);
  649. // n9_comm_dac_0x6010(idx);
  650. n9_comm_dac_0x1700(idx);
  651. // n9_comm_dac_0x0D57(idx);
  652. comm_stop_cal_dac_timing(comm);
  653. }